The present invention relates generally to a phase locked loop (PLL) and more particularly to a self biased multifrequency PLL.
Delay-locked loops (DLLs) and phase-locked loops (PLLs) are often used in the I/O interfaces of digital integrated circuits in order to hide clock distribution delays and to improve overall system timing. In these applications, DLLs and PLLs must closely track the input clock. However, the rising demand for high-speed I/O has created an increasingly noisy environment in which DLLs and PLLs must function. This noise, typically in the form of supply and substrate noise, tends to cause the output clocks of DLLs and PLLs to jitter from their ideal timing. With a shrinking tolerance for jitter in the decreasing period of the output clock, the design of low jitter DLLs and PLLs has become very challenging.
Achieving low jitter in PLL and DLL designs can be difficult due to a number of design tradeoffs. Consider a typical PLL which is based on a voltage controlled oscillator (VCO). The amount of input tracking jitter produced as a result of supply and substrate noise is directly related to how quickly the PLL can correct the output frequency. To reduce the jitter, the loop bandwidth should be set as high as possible. Unfortunately, the loop bandwidth is affected by many process technology factors and is constrained to be well below the lowest operating frequency for stability. These constraints can cause the PLL to have a narrow operating frequency range and poor jitter performance. Although a typical DLL is based on a delay line and thus simpler from a control perspective, it can have a limited delay range which leads to a set of problems similar to that of the PLL.
FIG. 1 illustrates a conventional phase locked loop (PLL) 10. PLL 10 comprises a phase frequency detector (PFD) 12 which receives a feedback frequency and a fixed reference frequency from typically a crystal oscillator. The phase frequency detector 12 provides two output signals, an up signal or a down signal depending on the relationship of the fixed frequency and the feedback frequency. Those signals are provided to charge pump 14 which provides an output to a low pass filter 16 and a voltage controlled oscillator (VCO) 18. The VCO 18 provides an output voltage based upon the frequency. The output voltage is fed back to a counter 20 which is typically a divide by N counter which is used to ensure loop stability. Accordingly, if the phase frequency detector 12 provides an up signal there will be a corresponding increase in the charge pump signal to the VCO 18 to cause the feedback frequency to increase to match it to the fixed frequency. Conversely, if the phase frequency detector 12 provides a down signal there will be a corresponding decrease in the charge pump signal to the VCO 18 which will cause the feedback frequency to decrease, thereby bringing it in line with the crystal.
As is well known, the open loop gain (GOL) of the PLL can be characterized by the following equation which is shown below:       G    ol    =            Ich      ·              K        0            ·              (                  1          +          RCs                )                    Cs      2      
As is well known, the closed loop gain (GCL) for PLL is then a second-order system as shown below:       G    cl    =                    G        ol                    1        +                              G            ol                    N                      =                            N          ·          Ich          ·                      K            0                    ·                      (                          1              +              RCs                        )                                                NCs            2                    +                      Ich            ·                          K              0                        ·                          (                              1                +                RCs                            )                                          =              N        ·                              1            +                          2              ·              ζ              ·                              (                                  s                  /                                      w                    n                                                  )                                                          1            +                          2              ·              ζ              ·                              (                                  s                  /                                      w                    n                                                  )                                      +                                          (                                  s                  /                                      w                    n                                                  )                            2                                          
The loop system can be characterized by two factors, the loop damping factor and the loop bandwidth factor.
The loop damping factor ("xgr") is characterized by the equation:   ζ  =                    RCw        n            2        =                  R        2            ⁢                                    Ich            ·                          K              0                        ·            C                    N                    
The loop bandwidth factor (wn) is characterized by the equation:       w    n    =                    Ich        ·                  K          0                    NC      
FIG. 2 is a Bode plot which illustrates the open loop gain (GOL) and the closed loop gain (GCL) for stable and unstable systems respectively. The traditional stability criteria for GOL for the PLL is Gol crossing 0 dB with a xe2x88x9220 db/decade slope so that                     w        n             greater than               w        RC              =          1      RC        ,                    then        ⁢                  xe2x80x83                ⁢        ζ             greater than                         0          ·          5                ⁢                  xe2x80x83                ⁢        because        ⁢                  xe2x80x83                ⁢                              w            n                                w            RC                                =                            w          c                          w          n                    =              2        ·        ζ            
The open loop gain GOL usually has a distant pole due to parasitic capacitances. Accordingly, the PLL can be unstable if appropriate precautions are not taken. Actually, the stability criteria is more restrictive if it""s deduced from differential equation (sampling) but the VCO overload criteria is usually prevailing. That is due to the instantaneous voltage drop on the loop filter.
FIG. 3 illustrates a change of Ich over time. It is known that the VCO overload limit is       R    ·    Ich     less than             Fvco              K        0              .  
This relationship leads to the following equation:             w      n              w      ref         less than             1              4        ⁢        πζ              .  
Accordingly, therefore, xcfx89ref must be at least 2.xcfx80 times away from xcfx89C to ensure stability. The optimum damping factor for a critically damped system stability having a minimum settling time is 0.707. So xcfx89ref then must be 8.88 times away from xcfx89n to ensure stability. A safe value for this relationship is that xcfx89ref is ten (10) times away from xcfx89n, to filter input frequency noise.
As before mentioned, achieving low jitter in PLL designs can be difficult due to a number of designs tradeoffs. To reduce peak-to-peak jitter due to VCO noise, it is advantageous to keep as high a PLL bandwidth as possible. Traditional charge-pump PLL design would keep the PLL bandwidth and damping factor sufficiently far away from stability limits under all variations of the input reference frequency, the manufacturing process, and the division ratio in the feedback path N. These constraints can cause the PLL to have a narrow operating frequency range and poor jitter performance.
Ideally, both "xgr" and       w    n        w    ref  
should be constant so that there is no limit on the operating frequency range and the jitter performance can be improved.
A self-biased PLL design technique avoids the necessity for external biasing (bandgap) by generating internal bias voltages and currents depending on the operating conditions. FIG. 4 illustrates a conventional self-biased PLL 100. In the self-biased system of FIG. 4, there is a similar phase frequency detector 101 with two charge pumps 102 and 106, one of which (charge pump 106) provides an output directly to the VCO 105 and the other of which (charge pump 102) provides its output to a low pass filter 103 which in turn provides a signal to a bias generator 104. The bias generator 104 in turn provides an output signal Vbn to the VCO 105, while the charge pump 106 provides an input to the VCO 105 of Vbp. The output V0 of the VCO 105 is fed back to a divide by N counter 108 in a manner similar to that described with reference to FIG. 1. The self-biased PLL design achieves process technology independence, fixed damping factor, fixed bandwidth to operating frequency ratio, broad frequency range, input phase offset cancellation, high supply and substrate noise rejection. Accordingly, this system is advantageous over the system of FIG. 1. However, it does have problems which will be described hereinbelow. Principally, those problems are associated with it being only allowed to operate effectively in a fixed frequency environment.
The following three papers describe some existing self-biased PLLs:
[1] Low-jitter Process-Independent DLL and PLL Based on Self-biased Techniques, John G. Maneatis, IEEE Journal of Solid State Circuits, Vol.31, No.11, November 1996.
[2] Adaptive Bandwidth DLLs and PLLs using Regulated Supply CMOS Buffers, S.Sidiropoulos, D.Liu, J.Kim, G.Wei, M.Horowitzxe2x80x94Rambus Inc. and Standford University, IEEE 2000.
[3] A 2-1600-MHz 1.2-2.5V CMOS Clock Recovery PLL with Feedback Phase-Selection and Averaging Phase-Interpolation for Jitter Reduction, Patrick Larsson, 1999 IEEE International Solid State Circuits Conference, Vol.34, No.12, December 1999.
As before mentioned, these solutions do not affect frequency range variations associated with N. They only provide a fixed bandwidth independent of the frequency range.
Accordingly, what is needed is a system and method for providing a PLL which can operate effectively over a wide range of frequencies. The system should be easy to implement in existing systems and be cost effective. The present invention addresses such a need.
A self-adaptive method for controlling a self-biased PLL system is disclosed. The method comprises providing an application-dependent input frequency; and providing an application-dependent number N representing the ratio between the output frequency and the application-dependent input frequency to the PLL system.
In a system and method in accordance with the present invention, the bandwidth and damping factor are tracked, not only with the input frequency but with the divider ratio as well. Therefore, jitter is minimized for any operating condition (i.e., input frequency variations associated with an application-dependent number N representing the ratio between the output frequency and the application-dependent input frequency to the PLL system). The charge-pump current is made to be proportional to the VCO current ID and inversely proportional to the frequency range associated with N; and the loop filter resistor is made to be inversely proportional to the square root of the VCO current ID and proportional to N. In so doing, the bandwidth and damping factors can be tracked more comprehensively.